scientific article; zbMATH DE number 1321108
Introductory exposition (textbooks, tutorial papers, etc.) pertaining to computer science (68-01) Parallel algorithms in computer science (68W10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Introductory exposition (textbooks, tutorial papers, etc.) pertaining to information and communication theory (94-01) Applications of graph theory to circuits and networks (94C15)
The basic purpose of the third edition is to investigate the new challenges presented by interconnect and process innovations. In particular, we wanted to identify key problems and research areas that physical design community needs to invest in order to meet the challenges. We took a task of presenting those ideas while maintaining the flavor of the book. As a result, we have added two new chapters and new material has been added to most of the chapters. A new chapter on process innovation and its impact on physical design has been added. Another focus of the book has been to promote use of Internet as a resource, so wherever possible URLs has been provided for further investigation. Chapters 1 and 2 have been updated. Chapter 3 is a new chapter on the fabrication process and its impact. Chapter 4 (algorithms) and Chapter 5 (partitioning) have been edited for clarity. Chapter on Floorplanning, Placement and Pin Assignment has been split into Chapter 6 (Floorplanning) and Chapter 7 (Placement) to bring sharper focus to floorplanning. New sequence pair algorithms have been added to Chapter 7 (Placement) Chapter 8 and 9 have been edited for clarity and references have been updated as appropriate. New sections have been added to Chapter 10, Chapter 11 and Chapter 12. In Chapter 10, we have added material related to performance driven routing. In Chapter 11, DME algorithm has been added. In Chapter 12, we have added new compaction algorithms. Chapters 13 (FPGAs) and 14 (MCMs) have been updated. We have made an attempt to update the bibliography quite extensively and many new items have been added. In summary, I have made an attempt to capture the impact of interconnect and process innovations on physical design flow. I have attempted to balance material on new innovations with the classical content of the 2nd edition (1995; Zbl 0840.68060) I hope that readers will find that information both useful and interesting.
- A tutorial on geometric programming
- On finding an empty staircase polygon of largest area (width) in a planar point-set
- Placement by thermodynamic simulated annealing
- On two generalized connectivities of graphs
- The generalized 3-connectivity of graph products
- Constructing edge-disjoint Steiner paths in lexicographic product networks
- The \(\lambda_3\)-connectivity and \(\kappa_3\)-connectivity of recursive circulants
- Conflict-free coloring of string graphs
- The \(\kappa_k\)-connectivity of line graphs
- Two lower bounds for generalized 3-connectivity of Cartesian product graphs
- Nordhaus-Gaddum-type results for the generalized edge-connectivity of graphs
- Efficient cell-based migration of VLSI layout
- A sharp lower bound for the generalized 3-edge-connectivity of strong product graphs
- On minimally 2-connected graphs with generalized connectivity \(\kappa_3=2\)
- An ILP based hierarchical global routing approach for VLSI ASIC design
- Packing strong subgraph in digraphs
- Path-connectivity of lexicographic product graphs
- Graphs with large generalized (edge-)connectivity
- Handbook of Algorithms for Physical Design Automation
- An algebraic multigrid-based algorithm for circuit clustering
- scientific article; zbMATH DE number 595444 (Why is no real title available?)
- scientific article; zbMATH DE number 802995 (Why is no real title available?)
- Improved bounds for colouring circle graphs
- A solution to a conjecture on the generalized connectivity of graphs
- Typical representatives of free homotopy classes in multi-punctured plane
- Generalized 3-edge-connectivity of Cartesian product graphs.
- Constructing internally disjoint pendant Steiner trees in Cartesian product networks
- Multiscale optimization in VLSI physical design automation
- Directed Steiner tree packing and directed tree connectivity
- Finding geometric representations of apex graphs is \textsf{NP}-hard
- Directed cycle k-connectivity of complete digraphs and complete regular bipartite digraphs
- The generalized 3-connectivity of exchanged crossed cube
- The generalized 3-connectivity of BCCC data center networks
- Combinatorics of rectangulations: old and new bijections
- On approximability of Steiner tree in _p-metrics
- Perfect out-forest problem and directed Steiner cycle packing problem
- On routing in VLSI design and communication networks
- Efficient preprocessing for VLSI optimization problems
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