An accurate performance model for network-on-chip and multicomputer interconnection networks

DOI10.1016/J.JPDC.2012.05.005zbMATH Open1248.68115OpenAlexW2059510900MaRDI QIDQ455994FDOQ455994

Authors: Slavko Gajin, Zoran Jovanovic 

Publication date: 23 October 2012

Published in: Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.jpdc.2012.05.005

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zbMATH Keywords

interconnection networkwormholeperformance modelingdeterministic routingnetwork on chip

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Distributed systems (68M14)

Cites Work

• Title not available (Why is that?)
• Introduction to algorithms
• Analytical modelling of wormhole-routed \(k\)-ary \(n\)-cubes in the presence of matrix-transpose traffic.
• A mathematical model of deterministic wormhole routing in hypercube multicomputers using virtual channels
• A performance model of adaptive wormhole routing in \(k\)-ary \(n\)-cubes in the presence of digit-reversal traffic
• Network performance under bimodal traffic loads
• Analysis of fully adaptive wormhole routing in tori
• An analytical model of adaptive wormhole routing with time-out
• Performance analysis of adaptive wormhole routing in a two-dimensional torus
• Communication delay in hypercubes in the presence of bit-reversal traffic

Cited In (9)

• A new modelling approach of wormhole-switched networks with finite buffers
• Performance modeling and prediction of nondedicated network computing
• A DTMC model for performance evaluation of irregular interconnection networks with asymmetric spatial traffic distributions
• A new approach to model virtual channels in interconnection networks
• Title not available (Why is that?)
• An analytical model for Network-on-Chip with finite input buffer
• On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip
• Analysis of a tandem network model of a single-router network-on-chip
• An accurate mathematical performance model of partially adaptive routing in binary \(n\)-cube multiprocessors

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