A Defect Tolerance Scheme for Nanotechnology Circuits

DOI10.1109/TCSI.2007.907875zbMATH Open1374.94960OpenAlexW2036360385MaRDI QIDQ4590263FDOQ4590263

Authors Ahmad Al-Yamani, Sundarkumar Ramsundar, Dhiraj K. Pradhan 

Publication date 20 November 2017

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tcsi.2007.907875

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (6)

• Tropical algebra based framework for error propagation analysis in systolic arrays
• System reduction for nanoscale IC design
• Towards effective exact methods for the maximum balanced biclique problem in bipartite graphs
• Defect-tolerance in cellular nanocomputers
• General swap-based multiple neighborhood adaptive search for the maximum balanced biclique problem
• New heuristic approaches for maximum balanced biclique problem

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