A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

DOI10.1109/TCSI.2012.2230506MaRDI QIDQ4956809zbMATH OpenFDO

Authors Chiu-Wing Sham, Xu Chen, Francis Chung-ming Lau, Yue Zhao, Wai Man Tam

Publication date 2 September 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://arxiv.org/abs/1305.0185

Mathematics Subject Classification ID

Convolutional codes (94B10) Decoding (94B35)

Abstract: This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than $10^{-13}$ at a bit-energy-to-noise-power-spectral-density ratio ($E_b/N_0$) of 3.55 dB.

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Cited in

(1)

• A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet

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