A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

DOI10.1109/TCSI.2012.2230506zbMATH Open1469.94165arXiv1305.0185MaRDI QIDQ4956809FDOQ4956809

Authors: Chiu-Wing Sham, Xu Chen, Francis Chung-ming Lau, Yue Zhao, Wai Man Tam 

Publication date: 2 September 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Abstract: This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than $10^{-13}$ at a bit-energy-to-noise-power-spectral-density ratio ($E_b/N_0$) of 3.55 dB.

Full work available at URL: https://arxiv.org/abs/1305.0185

Recommendations

• A Low Complexity-High Throughput QC-LDPC Encoder
• A High-Throughput LDPC Decoder Architecture With Rate Compatibility
• A Network-Efficient Nonbinary QC-LDPC Decoder Architecture
• Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes
• An Efficient Layered Decoding Architecture for Nonbinary QC-LDPC Codes
• High-speed \(\mathrm{RS}(255, 239)\) decoder based on LCC decoding
• Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes
• Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders

Mathematics Subject Classification ID

Convolutional codes (94B10) Decoding (94B35)

Cited In (1)

• A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet

This page was built for publication: A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4956809)