Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders

DOI10.1109/TCSI.2009.2026684MaRDI QIDQ5010993zbMATH OpenFDO

Authors Zhengang Chen, Tyler L. Brandon, Duncan G. Elliott, Stephen Bates, W. A. Krzymień, B. F. Cockburn

Publication date 26 August 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Mathematics Subject Classification ID

Convolutional codes (94B10) Decoding (94B35)

Cited in

(6)

• Joint Decoder Design for SSDs
• A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes
• An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation
• High performance word level sequential and parallel coding methods and architectures for bit plane coding
• A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
• Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture

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