A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes

DOI10.1109/TCSI.2010.2046964zbMATH Open1469.94167OpenAlexW2142321576MaRDI QIDQ5010935FDOQ5010935

Authors: Yeong-Luh Ueng, Chung-Jay Yang, Kuan-Chieh Wang, Chun-Jung Chen 

Publication date: 26 August 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2010.2046964

Recommendations

• An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding
• Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture
• A High-Throughput LDPC Decoder Architecture With Rate Compatibility
• VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
• Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis
• An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems
• Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders
• An iterative multiuser decoder for near-capacity communications

Mathematics Subject Classification ID

Decoding (94B35)

This page was built for publication: A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5010935)