An Algorithm to Generate Random Large Combinational Circuits

DOI10.1093/COMJNL/36.2.200MaRDI QIDQ5285455zbMATH OpenOpenAlexFDO

Authors C. C. Charlton, K. Halewood, Paul H. Leng, Paul E. Dunne

Publication date 29 June 1993

Published in The Computer Journal (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1093/comjnl/36.2.200

zbMATH Keywords

digital simulation systemslarge combinatorial circuitstestingVLSI

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

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(4)

• A heuristic method for generating large random expressions
• An algebraic technique for generating optimal CMOS circuitry in linear time
• Finding regularity: Describing and analysing circuits that are not quite regular
• Forecasting the efficiency of test generation algorithms for combinational circuits

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