Multistage interconnection networks in multiprocessor systems. A simulation study
From MaRDI portal
Publication:5323345
zbMATH Open1167.90421MaRDI QIDQ5323345FDOQ5323345
Authors: Victor López de Buen 
Publication date: 23 July 2009
Full work available at URL: https://eudml.org/doc/40124
Recommendations
- scientific article; zbMATH DE number 1726636
- MVAMIN: Mean value analysis algorithms for multistage interconnection networks
- Generating systems of equations for performance evaluation of multistage interconnection networks
- scientific article; zbMATH DE number 4029465
- Packet Switching Networks for Multiprocessors and Data Flow Computers
Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Communication networks in operations research (90B18)
Cited In (11)
- Performance analysis of the simultaneous optical multi-processor exchange bus
- Independent connections: An easy characterization of baseline-equivalent multistage interconnection networks
- Switching networks for SIMD multiprocessor computing systems (state-of- the-art review)
- Some new models for multiprocessor interconnection networks
- Title not available (Why is that?)
- Performance evaluation of singlestage and multistage interconnection networks connectivity in multiprocessors
- Title not available (Why is that?)
- Performance model for a prioritized multiple-bus multiprocessor system
- Packet Switching Networks for Multiprocessors and Data Flow Computers
- MVAMIN: Mean value analysis algorithms for multistage interconnection networks
- Performance evaluation of SNAIL: a multiprocessor based on the simple serial synchronized multistage interconnection network architecture
This page was built for publication: Multistage interconnection networks in multiprocessor systems. A simulation study
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5323345)
