Loop transformations, convexity, pruning and optimization
DOI10.1145/1926385.1926449zbMATH Open1284.68094OpenAlexW4231316372MaRDI QIDQ5408575FDOQ5408575
Authors: Louis-Noël Pouchet, Uday Bondhugula, Cédric Bastoul, Albert Cohen, J. Ramanujam, P. Sadayappan, Nicolas Vasilache
Publication date: 10 April 2014
Published in: Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1145/1926385.1926449
Recommendations
- PIT: a framework for effectively composing high-level loop transformations
- Semi-automatic composition of loop transformations for deep parallelism and memory hierarchies
- scientific article; zbMATH DE number 1218791
- Languages and Compilers for Parallel Computing
- Transforming complex loop nests for locality
Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Theory of compilers and interpreters (68N20) Mathematical problems of computer architecture (68M07)
Cited In (18)
- Integrating loop and data transformations for global optimization
- Superoptimization in LLVM
- Optimizing nested loops using local CPS conversion
- Title not available (Why is that?)
- Languages and Compilers for Parallel Computing
- Transforming complex loop nests for locality
- Title not available (Why is that?)
- PIT: a framework for effectively composing high-level loop transformations
- In search of a program generator to implement generic transformations for high-performance computing
- Euro-Par 2004 Parallel Processing
- Title not available (Why is that?)
- Randomized accuracy-aware program transformations for efficient approximate computations
- Euro-Par 2004 Parallel Processing
- Euro-Par 2004 Parallel Processing
- An efficient time-step-based self-adaptive algorithm for predictor-corrector methods of Runge-Kutta type
- Weight optimisation in \(\mathcal H_{\infty}\) loop-shaping
- A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details
- A methodology for speeding up loop kernels by exploiting the software information and the memory architecture
This page was built for publication: Loop transformations, convexity, pruning and optimization
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5408575)