Design of multiple-valued arithmetic circuits using counter tree diagrams

MaRDI QIDQ5446296zbMATH OpenFDO

Authors Naofumi Homma, Katsuhiko Degawa, Tatsuo Higuchi, Takafumi Aoki

Publication date 6 March 2008

zbMATH Keywords

arithmetic circuitsmultiple-valued logiccircuit optimizationaddersredundant number systemscurrent mode logic

Mathematics Subject Classification ID

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(3)

• Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer
• Design of multivalued shift-register type counter
• A formal approach to designing multiple-valued arithmetic circuits

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