Universal Address Sequence Generator for Memory Built-in Self-test*
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Publication:5880943
DOI10.3233/FI-222141zbMATH Open1506.68006arXiv2208.05325MaRDI QIDQ5880943FDOQ5880943
Authors: Ireneusz Mrozek, N. A. Shevchenko, Vyacheslav Yarmolik
Publication date: 9 March 2023
Published in: Fundamenta Informaticae (Search for Journal in Brave)
Abstract: This paper presents the universal address sequence generator (UASG) for memory built-in-self-test. The studies are based on the proposed universal method for generating address sequences with the desired properties for multirun march memory tests. As a mathematical model, a modification of the recursive relation for quasi-random sequence generation is used. For this model, a structural diagram of the hardware implementation is given, of which the basis is a storage device for storing so-called direction numbers of the generation matrix. The form of the generation matrix determines the basic properties of the generated address sequences. The proposed UASG generates a wide spectrum of different address sequences, including the standard ones, such as linear, address complement, gray code, worst-case gate delay, , next address, and pseudorandom. Examples of the use of the proposed methods are considered. The result of the practical implementation of the UASG is presented, and the main characteristics are evaluated.
Full work available at URL: https://arxiv.org/abs/2208.05325
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Cites Work
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- Title not available (Why is that?)
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- Multiple Controlled Random Testing*
- Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs
- Randomized Quasi-Random Testing
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