Analysis and synthesis of controlled delay lines for fast digital devices

DOI10.1134/S1064562409040474zbMATH Open1179.94081OpenAlexW2056154663MaRDI QIDQ5897030FDOQ5897030

Authors: G. A. Leonov 

Publication date: 5 February 2010

Published in: Doklady Mathematics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1134/s1064562409040474

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Mathematics Subject Classification ID

Feedback control (93B52) Application models in control theory (93C95) Analytic circuit theory (94C05)

Cites Work

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Cited In (3)

• Analysis and synthesis of clock generator
• Analysis and synthesis of controlled delay lines for fast digital devices
• Analysis and synthesis of controlled delay lines

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