Correct Hardware Design and Verification Methods

DOI10.1007/B93958zbMATH Open1179.68080OpenAlexW219731125MaRDI QIDQ5897060FDOQ5897060

Authors: Hana Chockler, Orna Kupferman, Moshe Y. Vardi 

Publication date: 5 February 2010

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/b93958

Recommendations

• Coverage metrics for temporal logic model checking
• scientific article; zbMATH DE number 1701778
• scientific article; zbMATH DE number 1796124
• Empirical software metrics for benchmarking of verification tools

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60)

Cited In (6)

• A quantitative completeness analysis for property sets
• Title not available (Why is that?)
• Title not available (Why is that?)
• Title not available (Why is that?)
• Coverage metrics for temporal logic model checking
• Before and after vacuity

This page was built for publication: Correct Hardware Design and Verification Methods

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5897060)