Correct Hardware Design and Verification Methods

DOI10.1007/B93958zbMATH Open1179.68088OpenAlexW219731125MaRDI QIDQ5897075FDOQ5897075

Panagiotis Manolios

Publication date: 5 February 2010

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/b93958

Recommendations

• Branching time and abstraction in bisimulation semantics
• Branching within time: An expressively complete and elementarily decidable temporal logic for time granularity
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• scientific article; zbMATH DE number 1751887
• A note about the axioms for branching-time logic
• Ranked Predicate Abstraction for Branching Time: Complete, Incremental, and Precise
• Abstraction for branching time properties.
• Axioms for Branching Time
• The temporal logic of branching time

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cited In (7)

• Universal extensions to simulate specifications
• Twenty years of rewriting logic
• Simulation refinement for concurrency verification
• Expressive completeness failure in branching time structures
• Specification and verification of concurrent programs through refinements
• A framework for verifying bit-level pipelined machines based on automated deduction and decision procedures
• Algebraic simulations

Uses Software

• SATO
• Chaff

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