FPGA architecture and implementation of sparse matrix-vector multiplication for the finite element method

DOI10.1016/J.CPC.2007.11.014zbMATH Open1196.65084OpenAlexW2164261830MaRDI QIDQ710265FDOQ710265

Authors: D. Kharzeev 

Publication date: 18 October 2010

Published in: Computer Physics Communications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.cpc.2007.11.014

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zbMATH Keywords

FEMFPGA

Mathematics Subject Classification ID

Computational methods for sparse matrices (65F50) Complexity and performance of numerical algorithms (65Y20)

Cites Work

• SPAR: a new architecture for large finite element computations
• Parallel solution of linear systems with striped sparse matrices
• Processor-efficient sparse matrix-vector multiplication
• Determination of Stripe Structures for Finite Element Matrices
• Title not available (Why is that?)

Cited In (8)

• Sparse Cholesky factorization on FPGA using parameterized model
• High-Performance Mixed-Precision Linear Solver for FPGAs
• Analysis of the basic implementation aspects of hardware-accelerated density functional theory calculations
• FPGA implementation of ECT digital system for imaging conductive materials
• FPGA computation of the 3D heat equation
• Towards an FPGA solver for the PageRank eigenvector problem
• Run-time-reconfigurable multi-precision floating-point matrix multiplier intellectual property core on FPGA
• Title not available (Why is that?)

Uses Software

• SPAR

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