Stepwise-overlapped parallel annealing and its application to floorplan designs

DOI10.1016/0010-4485(91)90004-GMaRDI QIDQ756935zbMATH OpenFDO

Authors Youngtak Kim, Youngjo Jang, Myunghwan Kim

Publication date 1991

Published in CAD. Computer-Aided Design (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0010-4485(91)90004-G

zbMATH Keywords

combinatorial optimizationfloorplan design of VLSI circuitsglobal optimizationnumerical resultsparallel computationsimulated annealing algorithmtravelling salesman problem

Mathematics Subject Classification ID

Numerical mathematical programming methods (65K05) Parallel numerical computation (65Y05) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Integer programming (90C10) Combinatorial optimization (90C27)

Review text

The authors propose a parallel version of the simulated annealing algorithm. They use the idea of decomposition by Markov chains, i.e. the Markov chain used in the simulated annealing algorithm is truncated and decomposed into subchains, each of them being associated to a processor. They discuss the strategy for reducing the temperature and give encouraging numerical results on the travelling salesman problem. They also apply the algorithm to the floorplan design of VLSI circuits.

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