Reconfiguring Arrays with Faults Part I: Worst-Case Faults

DOI10.1137/S0097539793255011MaRDI QIDQ4376192zbMATH OpenOpenAlexFDO

Authors Bruce M. Maggs, Ramesh K. Sitaraman, Richard Cole

Publication date 10 February 1998

Published in SIAM Journal on Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1137/s0097539793255011

zbMATH Keywords

array-based networkfault tolerancemesh networknetwork emulation

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Network design and communication in computer systems (68M10) Reliability, testing and fault tolerance of networks and computer systems (68M15) Formal languages and automata (68Q45)

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(9)

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• Catastrophic faults in reconfigurable systolic linear arrays
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• Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays
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• A local and dynamic algorithm for reconfiguring a faulty processor array into a maximal fault-free subarray
• On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy
• Fault tolerance in autonomous acoustic arrays

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