Response compaction for system-on-a-chip based on advanced convolutional codes

DOI10.1007/S11432-006-0262-0MaRDI QIDQ882714zbMATH OpenOpenAlexWikidataFDO

Authors Yinhe Han, Huawei Li, Chandra Anshuman, Xiaowei Li

Publication date 24 May 2007

Published in Science in China. Series F (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s11432-006-0262-0

Mathematics Subject Classification ID

Convolutional codes (94B10)

Review text

This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a \((n, n-1, m, 3)\) convolutional code is presented. When the proposed theorems are satisfied, the compactor can avoid two and any odd erroneous bits cancellations, and handle one unknown bit (X bit). When the X bits in response are clustered, multiple-weight check matrix design algorithm can be used to reduce the effect of massive X bits. Some extended experimental results show that the proposed encoder has an acceptable-level X tolerant capacity and low error cancellations probability.

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Cites work

• Convolutional codes I: Algebraic structure
• On cyclic convolutional codes
• Programmable BIST space compactors

Cited in

(3)

• Compaction of test response at self-testing in the programmable logic matrices
• Two level core test compression based on partial test vector reuse and VRL coding
• Application of group and expansion code in test data compression

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