Robust clock generation system

DOI10.1080/00207170600913265MaRDI QIDQ3426414zbMATH OpenOpenAlexFDO

Authors Ricardo B. N. M. Pinheiro, J. J. Da Cruz, José Roberto C. Piqueira

Publication date 8 March 2007

Published in International Journal of Control (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1080/00207170600913265

zbMATH Keywords

robust controltime signals

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10) Design techniques (robust design, computer-aided design, etc.) (93B51)

Recommendations

• Processing and transmission of timing signals in synchronous networks
• Control of clock signals
• Design constraints for third-order PLL nodes in master-slave clock distribution networks
• Delay-free phase-locked loop ring: equilibrium and phase perturbation
• Networked control under time-synchronization errors

Cites work

• Multivariable feedback design: Concepts for a classical/modern synthesis
• Robustness with observers

Cited in

(5)

• Delay-free phase-locked loop ring: equilibrium and phase perturbation
• Control of clock signals
• Analysis and synthesis of clock generator
• Processing and transmission of timing signals in synchronous networks
• Linear approach for synchronous state stability in fully connected PLL networks

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