SHA-3 on ARM11 processors

DOI10.1007/978-3-642-31410-0_20MaRDI QIDQ2900631zbMATH OpenOpenAlexFDO

Authors Peter Schwabe, Bo-Yin Yang, Shang-Yi Yang

Publication date 23 July 2012

Published in Progress in Cryptology - AFRICACRYPT 2012 (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-31410-0_20

zbMATH Keywords

ARM processorsSHA-3software implementation

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

Recommendations

• Performance analysis of the SHA-3 candidates on exotic multi-core architectures
• The Intel AES instructions set and the SHA-3 candidates
• Throughput vs. area trade-offs in high-speed architectures of five round 3 SHA-3 candidates implemented using Xilinx and Altera FPGAs
• Lightweight implementations of SHA-3 candidates on FPGAs
• Efficient Vector Implementations of AES-Based Designs: A Case Study and New Implemenations for Grøstl

Describes a project that uses

Uses Software

• eBASH

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