Simplifying circuits for formal verification using parametric representation

DOI10.1007/3-540-36126-X_4MaRDI QIDQ4427895zbMATH OpenFDO

Authors I. H. Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl P. Pixley

Publication date 14 September 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2517/25170052.htm

Mathematics Subject Classification ID

Computer science aspects of computer-aided design (68U07)

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Cited in

(5)

• Simplification in a satisfiability checker for VLSI applications
• Building circuits from relations
• A probabilistic and approximated approach to circuit-based formal verification
• Correct Hardware Design and Verification Methods
• Equivalence checking of circuits with parameterized specifications

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Uses Software

• Chaff

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