Simulation and generation of IDDQ tests for bridging faults in combinational circuits

DOI10.1109/12.543707MaRDI QIDQ4420830zbMATH OpenOpenAlexFDO

Authors Sreejit Chakravarty, Paul J. Thadikaran

Publication date 1996

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.543707

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)

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(4)

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• A systematic technique for detecting and locating bridging and stuck-at faults in I/O pins of LSI/VLSI chips
• A Practical Approach to Fault Simulation and Test Generation for Bridging Faults
• A sweeping line approach to interconnect testing

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