SATIRE

swMATH4648MaRDI QIDQ16818FDOQ16818

Author name not available (Why is that?)

Cited In (36)

• Hardware and Software, Verification and Testing
• Towards a Design Flow for Reversible Logic
• Combining Abstraction Refinement and SAT-Based Model Checking
• Linear Encodings of Bounded LTL Model Checking
• Mining Backbone Literals in Incremental SAT
• Correct Hardware Design and Verification Methods
• Gearing Up for Effective ASP Planning
• Computer Aided Verification
• On dedicated CDCL strategies for PB solvers
• The incremental satisfiability problem for a two conjunctive normal form
• SYSTEMATIC VERSUS LOCAL SEARCH AND GA TECHNIQUES FOR INCREMENTAL SAT
• Title not available (Why is that?)
• On weakening strategies for PB solvers
• Computer Aided Verification
• Formal Methods for Hardware Verification
• Test Pattern Generation using Boolean Proof Engines
• A framework for satisfiability modulo theories
• On SAT instance classes and a method for reliable performance experiments with SAT solvers
• Incomplete dynamic backtracking for linear pseudo-Boolean problems
• Range and set abstraction using SAT
• Ultimately Incremental SAT
• Title not available (Why is that?)
• An approach for extracting a small unsatisfiable core
• Title not available (Why is that?)
• Theory and Applications of Satisfiability Testing
• A rigorous methodology for specification and verification of business processes
• Formal Methods in Computer-Aided Design
• Incremental bounded model checking for embedded software
• HySAT: An efficient proof engine for bounded model checking of hybrid systems
• High Quality Test Pattern Generation and Boolean Satisfiability
• Preprocessing in Incremental SAT
• Search techniques for SAT-based Boolean optimization
• Automatic Evaluation of Context-Free Grammars (System Description)
• Decision procedures. An algorithmic point of view
• Title not available (Why is that?)
• Transfer function synthesis without quantifier elimination

This page was built for software: SATIRE