Cited in
(22)- Robust online monitoring of signal temporal logic
- A brief account of runtime verification
- On simulation-based probabilistic model checking of mixed-analog circuits
- Algorithms for monitoring real-time properties
- Formal system verification. State-of the-art and future trends
- STL*: extending signal temporal logic with signal-value freezing operator
- ModelPlex: verified runtime validation of verified cyber-physical system models
- FoCs
- PASS
- S-TaLiRo
- Delta Sigma
- Rapture
- Breach
- Copilot
- iscasMc
- ASDeX
- POWER-TRUCTOR
- On temporal logic constraint solving for analyzing numerical data time series
- Runtime enforcement of timed properties revisited
- Localizing Faults in Simulink/Stateflow Models with STL
- Continuous valuations of temporal logic specifications with applications to parameter optimization and robustness measures
- Analog property checkers: a DDR2 case study
This page was built for software: AMT
