Some combinatorial optimization problems arising from VLSI circuit design

DOI10.1007/BF02662005MaRDI QIDQ1319148zbMATH OpenFDO

Authors Yanpei Liu

Publication date 12 April 1994

Published in Applied Mathematics. Series B (English Edition) (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/BF02662005

zbMATH Keywords

combinatorial optimizationforbidden configurationrectilinear convexityrectilinear embeddingVLSI circuit design

Mathematics Subject Classification ID

Planar graphs; geometric and topological aspects of graph theory (05C10) Graph theory (including graph drawing) in computer science (68R10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Combinatorial optimization (90C27) Applications of graph theory to circuits and networks (94C15)

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Cites work

• A Separator Theorem for Planar Graphs
• At most single-bend embeddings of cubic graphs
• On-line 2-satisfiability
• The efficient recognition on net-extensibility of graphs
• Theoretical results on at most 1-bend embeddability of graphs

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