Entity usage

This page lists pages that use the given entity (e.g. Q42). The list is sorted by descending page ID, so that newer pages are listed first.

Showing below up to 50 results in range #1 to #50.

Integrating ADTs in KeY and their application to history-based reasoning about collection: Label: en
Fingerprinting and analysis of Bluetooth devices with automata learning: Label: en
Runtime verification of real-time event streams using the tool HStriver: Label: en
Preface for the formal methods in system design special issue on `Formal Methods 2021': Label: en
Symbolic encoding of LL(1) parsing and its applications: Label: en
Church synthesis on register automata over linearly ordered data domains: Label: en
Dissecting \texttt{ltlsynt}: Label: en
\textsc{Synbit}: synthesizing bidirectional programs using unidirectional sketches: Label: en
Enhancing active model learning with equivalence checking using simulation relations: Label: en
Finite-trace and generalized-reactivity specifications in temporal synthesis: Label: en
Preface for the formal methods in system design special issue on SYNT 2021: Label: en
Concise outlines for a complex logic: a proof outline checker for TaDA: Label: en
The probabilistic termination tool amber: Label: en
Reluplex: a calculus for reasoning about deep neural networks: Label: en
Static detection of uncoalesced accesses in GPU programs: Label: en
Distributed parametric model checking timed automata under non-zenoness assumption: Label: en
Compositional runtime enforcement revisited: Label: en
From LTL to rLTL monitoring: improved monitorability through robust semantics: Label: en
Automated repair for timed systems: Label: en
Relational abstract interpretation of arrays in assembly code: Label: en
Equivalence checking and intersection of deterministic timed finite state machines: Label: en
Bridging the gap between single- and multi-model predictive runtime verification: Label: en
Cut-off theorems for the \textit{PV}-model: Label: en
The complexity gap in the static analysis of cache accesses grows if procedure calls are added: Label: en
Correction to: ``Parameterized verification of leader/follower systems via first-order temporal logic: Label: en
Assumption-based runtime verification: Label: en
Specifiable robustness in reactive synthesis: Label: en
Functional synthesis via input-output separation: Label: en
LTL model checking of self modifying code: Label: en
Control strategies for off-line testing of timed systems: Label: en
Interpolation with guided refinement: revisiting incrementality in SAT-based unbounded model checking: Label: en
Verification Modulo theories: Label: en
Machine learning and logic: a new frontier in artificial intelligence: Label: en
On monitoring linear temporal properties: Label: en
Mining definitions in Kissat with Kittens: Label: en
SMT-based verification of program changes through summary repair: Label: en
Achieving high coverage in hardware equivalence checking via concolic verification: Label: en
Obituary: Edmund Melson Clarke jun. (1945--2020): Label: en
Introduction to the special issue on runtime verification: Label: en
Finite-trace linear temporal logic: coinductive completeness: Label: en
Quantitative monitoring of STL with edit distance: Label: en
Wireless protocol validation under uncertainty: Label: en
On the complexity of monitoring Orchids signatures, and recurrence equations: Label: en
Towards efficient verification of population protocols: Label: en
Decentralised LTL monitoring: Label: en
Exploiting interleaving semantics in symbolic state-space generation: Label: en
Learning to verify branching time properties: Label: en
Refinement preserving approximations for the design and verification of heterogeneous systems: Label: en
An algebraic theory for behavioral modeling and protocol synthesis in system design: Label: en
Concurrency in synchronous systems: Label: en