Pages that link to "Item:Q1102258"

The following pages link to Compiling communicating processes into delay-insensitive VLSI circuits (Q1102258):

Displaying 16 items.

• Reconciling fault-tolerant distributed computing and systems-on-chip (Q424907) (← links)
• CTRL: extension of CTL with regular expressions and fairness operators to verify genetic regulatory networks (Q548484) (← links)
• Asynchronous datapaths and the design of an asynchronous adder (Q685122) (← links)
• A formal approach to designing delay-insensitive circuits (Q808286) (← links)
• Revisiting sequential composition in process calculi (Q890611) (← links)
• On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP (Q1001805) (← links)
• Program refinement in fair transition systems (Q1323314) (← links)
• Retargeting a hardware compiler using protocol converters (Q1914042) (← links)
• Rewriting semantics of production rule sets (Q1931912) (← links)
• Compositional verification of asynchronous concurrent systems using CADP (Q2350492) (← links)
• A new explanation of the glitch phenomenon (Q2641279) (← links)
• Reflections on the Future of Concurrency Theory in General and Process Calculi in Particular (Q2870196) (← links)
• Elasticity and Petri Nets (Q3599221) (← links)
• Verification of asynchronous circuits by BDD-based model checking of Petri nets (Q5096372) (← links)
• Calculational derivation of a counter with bounded response time and bounded power dissipation (Q5136989) (← links)
• Asynchronous Logic Circuits and Sheaf Obstructions (Q5179025) (← links)