The following pages link to Massimo Alioto (Q3075929):
Displayed 14 items.
- Simple and accurate modeling of the output transition time in nanometer CMOS gates (Q3075931) (← links)
- Modelling of source-coupled logic gates (Q3149541) (← links)
- An efficient implementation of PRNGs based on the digital sawtooth map (Q3156960) (← links)
- Modelling and design considerations on CML gates under high-current effects (Q3372408) (← links)
- A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map (Q4590172) (← links)
- A feedback strategy to improve the entropy of a chaos-based random bit generator (Q4590480) (← links)
- Power-delay optimization of D-latch/MUX source coupled logic gates (Q4655741) (← links)
- Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read (Q4956746) (← links)
- Variations in Nanometer CMOS Flip-Flops: Part II—Energy Variability and Impact of Other Sources of Variations (Q5007715) (← links)
- Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing (Q5007937) (← links)
- Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial (Q5008661) (← links)
- Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits (Q5010970) (← links)
- A simple strategy for optimized design of one-level carry-skip adders (Q5349612) (← links)
- Modeling and Evaluation of Positive-Feedback Source-Coupled Logic (Q5362874) (← links)