Pages that link to "Item:Q4420928"
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The following pages link to A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach (Q4420928):
Displayed 5 items.
- Novel designs of nanometric parity preserving reversible compressor (Q488150) (← links)
- Computer arithmetic and hardware: ``off the shelf'' microprocessors versus ``custom hardware'' (Q1603886) (← links)
- The delay of circuits whose inputs have specified arrival times (Q2370422) (← links)
- On design of parity preserving reversible adder circuits (Q2400197) (← links)
- Implementation Studies of Multi-rate Systems (Q5232097) (← links)
