The Error Latency of a Fault in a Sequential Digital Circuit

DOI10.1109/TC.1976.1674668MaRDI QIDQ4101731zbMATH OpenOpenAlexFDO

Authors John J. Shedletsky, Edward J. McCluskey

Publication date 1976

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1976.1674668

Mathematics Subject Classification ID

Cited in

(4)

• Estimating the latent time of fault detection in finite automaton tested in real time
• Markov reliability models of fault-tolerant distributed computing systems
• Optimal periodic testing policy for circuit with self-testing
• MODIFIED TRANSITION MATRIX AND FAULT TESTING IN SEQUENTIAL LOGIC CIRCUITS UNDER RANDOM STIMULI WITH A SPECIFIED MEASURE OF CONFIDENCE

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