VLSI planarization. Methods, models, implementation

MaRDI QIDQ4377606zbMATH OpenFDO

Authors Valeriĭ Zalmanovich Feĭnberg, A. G. Levin, E. B. Rabinovich

Publication date 18 February 1998

zbMATH Keywords

algorithmEDA toolsembeddinggraphhypergraphplanarSteiner problemtopological approachVLSI design

Mathematics Subject Classification ID

Research exposition (monographs, survey articles) pertaining to computer science (68-02) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Review text

VLSI planarization is one of the basic stages of the so-called topological approach to VLSI design. This book considers the intense recent development in this field. Although it features an analysis of the problem, and the results of different authors are classified and generalized, this volume is mainly based on the investigations conducted by the present authors. The theory and methods discussed here may be applied to printed-circuit boards, hybrid circuits, etc. The book concentrates on hypergraph models of electric circuits and their planarization techniques. It will be of interest to EDA tools developers and to theoretical and applied mathematicians whose work involves VLSI design, algorithms, graph theory and complexity theory.

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Cited in

(3)

• The VLSI layout problem in various embedding models
• The role of twins in computing planar supports of hypergraphs
• On supports for graphs of bounded genus

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