The VLSI layout problem in various embedding models

DOI10.1007/3-540-53832-1_38MaRDI QIDQ4028111zbMATH OpenFDO

Authors Michael Formann, F. Wagner

Publication date 28 March 1993

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/3-540-53832-1_38

zbMATH Keywords

embedding modelsknock-knee modelManhattan modelNP-completenessroutingVLSI layout

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Graph theory (including graph drawing) in computer science (68R10) Applications of graph theory to circuits and networks (94C15)

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Cited in

(21)

• Paths, flows, and VLSI-layout. Proceedings of a meeting held from June 20 to July 1, 1988, at the University of Bonn, Germany
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• Optimal two-sided embeddings of complete binary trees in rectangular grids
• Separator-based graph embedding into multidimensional grids with small edge-congestion
• Complexity dichotomy on degree-constrained VLSI layouts with unit-length edges
• Relating bends and size in orthogonal graph drawings
• scientific article; zbMATH DE number 3938571 (Why is no real title available?)
• An Array Layout Methodology for VLSI Circuits
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• The net adding problem
• scientific article; zbMATH DE number 833244 (Why is no real title available?)
• Maximum area axis-aligned square packings
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