Efficient VLSI fault simulation (Q1203708): Difference between revisions

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+The Complexity of Fault Detection Problems for Combinational Logic Circuits
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+Test Routines Based on Symbolic Logical Statements
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+Multi-threshold threshold elements
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+Q5617282
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+The Weighted Random Test-Pattern Generator
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+Random Pattern Testability
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+Bounding Signal Probabilities in Combinational Circuits
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+Efficiency of Random Compact Testing
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+Q5684568
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+Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
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+Logic Test Pattern Generation Using Linear Codes
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+A Deductive Method for Simulating Faults in Logic Circuits
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+Diagnosis of Automata Failures: A Calculus and a Method
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+Comparison of Parallel and Deductive Fault Simulation Methods
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+Functional Partitioning and Simulation of Digital Circuits
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+LSI logic testing — An overview
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+Boolean Differential Calculus and its Application to Switching Theory
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+Boolean calculus of differences
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+Q5684964
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+Analyzing Errors with the Boolean Difference
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+The complexity of partial derivatives
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+Q4065051
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+Q3326832
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