Entity usage

This page lists pages that use the given entity (e.g. Q42). The list is sorted by descending page ID, so that newer pages are listed first.

Showing below up to 50 results in range #51 to #100.

Assumption-based runtime verification: Label: en
Specifiable robustness in reactive synthesis: Label: en
Functional synthesis via input-output separation: Label: en
LTL model checking of self modifying code: Label: en
Control strategies for off-line testing of timed systems: Label: en
Interpolation with guided refinement: revisiting incrementality in SAT-based unbounded model checking: Label: en
Verification Modulo theories: Label: en
Machine learning and logic: a new frontier in artificial intelligence: Label: en
On monitoring linear temporal properties: Label: en
Mining definitions in Kissat with Kittens: Label: en
SMT-based verification of program changes through summary repair: Label: en
Achieving high coverage in hardware equivalence checking via concolic verification: Label: en
Obituary: Edmund Melson Clarke jun. (1945--2020): Label: en
Introduction to the special issue on runtime verification: Label: en
Finite-trace linear temporal logic: coinductive completeness: Label: en
Quantitative monitoring of STL with edit distance: Label: en
Wireless protocol validation under uncertainty: Label: en
On the complexity of monitoring Orchids signatures, and recurrence equations: Label: en
Towards efficient verification of population protocols: Label: en
Decentralised LTL monitoring: Label: en
Exploiting interleaving semantics in symbolic state-space generation: Label: en
Learning to verify branching time properties: Label: en
Refinement preserving approximations for the design and verification of heterogeneous systems: Label: en
An algebraic theory for behavioral modeling and protocol synthesis in system design: Label: en
Concurrency in synchronous systems: Label: en
A predictive synchronizer for periodic clock domains: Label: en
A framework for modeling the distributed deployment of synchronous designs: Label: en
Reasoning about synchronization in GALS systems: Label: en
Compositional SCC analysis for language emptiness: Label: en
Model checking with strong fairness: Label: en
An algorithm for strongly connected component analysis in \(n \log n\) symbolic steps: Label: en
Special issue: 1st international workshop on runtime verification (RV'01). Selected papers based on the presentation at the workshop, Paris, France, July 23, 2001.: Label: en
Verification of parametric concurrent systems with prioritised FIFO resource management: Label: en
A congruence relation for sPBC: Label: en
Constructing invariants for hybrid systems: Label: en
Abstractions for hybrid systems: Label: en
Optimal infinite scheduling for multi-priced timed automata: Label: en
Special issue: Selected papers based on the presentations at the 7th international conference on hybrid systems and control (HSCC 2004), Philadelphia, USA, March 25--27, 2004.: Label: en
Memory model sensitive bytecode verification: Label: en
The word problem for visibly pushdown languages described by grammars: Label: en
Finding optimal hardware/software partitions: Label: en
Design and results of the 2nd annual satisfiability modulo theories competition (SMT-COMP 2006): Label: en
Checking extended CTL properties using guarded quotient structures: Label: en
SMT proof checking using a logical framework: Label: en
Being careful about theory combination: Label: en
SMT-based scenario verification for hybrid systems: Label: en
Symbolic backward reachability with effectively propositional logic. Application to security policy analysis: Label: en
Efficiently solving quantified bit-vector formulas: Label: en
Preface to the special issue ``SI: satisfiability modulo theories: Label: en
Efficient data race detection for async-finish parallelism: Label: en