Side-channel resistant crypto for less than 2,300 GE

DOI10.1007/s00145-010-9086-6zbMath1239.94063MaRDI QIDQ656520

Huaxiong Wang, San Ling, Axel Poschmann, Amir Moradi, Chu-Wee Lim, Khoongming Khoo

Publication date: 18 January 2012

Published in: Journal of Cryptology (Search for Journal in Brave)

Full work available at URL: http://hdl.handle.net/10220/7712

zbMATH Keywords

secret sharing; ASIC; side-channel attacks; countermeasures; lightweight

Mathematics Subject Classification ID

94A60: Cryptography

94A62: Authentication, digital signatures and secret sharing

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Uses Software

• PRESENT
• HIGHT
• mCrypton

Cites Work

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• How to share a secret
• Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
• DPA Leakage Models for CMOS Logic Circuits
• HIGHT: A New Block Cipher Suitable for Low-Resource Device
• New Lightweight DES Variants
• PRESENT: An Ultra-Lightweight Block Cipher
• Threshold Implementations Against Side-Channel Attacks and Glitches
• Ultra-Lightweight Implementations for Smart Devices – Security for 1000 Gate Equivalents
• On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoq Code Hopping Scheme
• Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
• A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
• Power Analysis Attacks
• Cryptographic Hardware and Embedded Systems - CHES 2004
• Cryptographic Hardware and Embedded Systems - CHES 2004
• Authenticating Pervasive Devices with Human Protocols
• Fast Software Encryption
• Applied Cryptography and Network Security