Topics in Cryptology – CT-RSA 2005

From MaRDI portal
Revision as of 04:43, 7 March 2024 by Import240305080351 (talk | contribs) (Created automatically from import240305080351)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

Publication:5710844

DOI10.1007/b105222zbMath1079.94561OpenAlexW2476332689MaRDI QIDQ5710844

Thomas Popp, Stefan Mangard, Berndt M. Gammel

Publication date: 8 December 2005

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/b105222




Related Items (27)

Monomial evaluation of polynomial functions protected by threshold implementations -- with an illustration on AES -- extended versionTowards tight random probing securityHomomorphic \(\mathrm {SIM}^2\)D operations: single instruction much more dataEnabling 3-Share Threshold Implementations for all 4-Bit S-BoxesMasking Tables—An Underestimated Security RiskHigher-Order Glitch Resistant Implementation of the PRESENT S-BoxMasking and leakage-resilient primitives: one, the other(s) or both?Effective and efficient masking with low noise using small-Mersenne-prime ciphersHandcrafting: improving automated masking in hardware with manual optimizations\texttt{POLKA}: towards leakage-resistant post-quantum CCA-secure public key encryptionUnknown-Input Attacks in the Parallel Setting: Improving the Security of the CHES 2012 Leakage-Resilient PRFHigher-order masking scheme for Trivium hardware implementationBridging the gap: advanced tools for side-channel leakage estimation beyond Gaussian templates and histogramsLearning with physical rounding for linear and quadratic leakage functionsAn Efficient Side-Channel Protected AES Implementation with Arbitrary Protection OrderSecure hardware implementation of nonlinear functions in the presence of glitchesParallel Implementations of Masking Schemes and the Bounded Moment Leakage ModelCodes for Side-Channel Attacks and ProtectionsMaking masking security proofs concrete (or how to evaluate the security of any leaking device), extended versionSecure Hardware Implementation of Non-linear Functions in the Presence of GlitchesPolynomial Evaluation and Side Channel AnalysisDesign of a Differential Power Analysis Resistant Masked AES S-BoxPractical Attacks on Masked HardwareFault Analysis Attack against an AES Prototype Chip Using RSLTowards Sound Fresh Re-keying with Hard (Physical) Learning ProblemsParTI – Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection AttacksMode-level vs. implementation-level physical security in symmetric cryptography. A practical guide through the leakage-resistance jungle







This page was built for publication: Topics in Cryptology – CT-RSA 2005