A Network-Efficient Nonbinary QC-LDPC Decoder Architecture

DOI10.1109/TCSI.2011.2177001MaRDI QIDQ5008828zbMATH OpenFDO

Authors Chuan Zhang, Keshab K. Parhi

Publication date 26 August 2021

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TCSI.2011.2177001

Mathematics Subject Classification ID

Decoding (94B35)

Cited in

(4)

• An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation
• A Flexible NISC-Based LDPC Decoder
• A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
• Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture

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