A parallel transitive closure computation algorithm for VLSI test generation

DOI10.1007/3-540-48051-X_25MaRDI QIDQ3046401zbMATH OpenFDO

Authors Seema Bawa, G. K. Sharma, G. Sharma

Publication date 12 August 2004

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2367/23670243.htm

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Computing methodologies and applications (68U99) Parallel algorithms in computer science (68W10) Fault detection; testing in circuits and networks (94C12)

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Cited in

(4)

• An adaptive heuristic algorithm for VLSI test vectors selection
• Parallel VLSI test in a shared-memory multiprocessor
• On computing transitive-closure equivalence sets using a hybrid GA-DP approach
• Coarse-grain parallelization of test vectors generation on multiprocessor systems

Describes a project that uses

Uses Software

• PVM

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