Parallel VLSI test in a shared-memory multiprocessor

DOI10.1002/1096-9128(20000425)12:5%3C311::AID-CPE492%3E3.0.CO;2-QMaRDI QIDQ2777814zbMATH OpenOpenAlexFDO

Authors C. Gil, J. Ortega, M. G. Montoya

Publication date 7 March 2002

Published in Concurrency: Practice and Experience (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1002/1096-9128(20000425)12:5%3C311::aid-cpe492%3E3.0.co;2-q

zbMATH Keywords

distributed-memory multicomputerVLSI test

Mathematics Subject Classification ID

Computer system organization (68M99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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Cites work

• An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
• Families of Reed-Muller canonical forms

Cited in

(8)

• Test schedules for VLSI circuits having built-in test hardware
• A parallel system for test pattern generation
• Optimization of parallel-series self-testing for discrete devices
• A hybrid meta-heuristic for multi-objective optimization: MOSATS
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• Computational Science and Its Applications – ICCSA 2004

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