A signed binary addition circuit based on an alternative class of addition tables

DOI10.1016/S0045-7906(01)00027-1MaRDI QIDQ1860062zbMATH OpenOpenAlexWikidataFDO

Authors Mitch Thornton

Publication date 20 February 2003

Published in Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0045-7906(01)00027-1

zbMATH Keywords

high speed addition circuitryredundant number systemssigned binary additionsigned digit number systems

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computer system organization (68M99) Computing methodologies and applications (68U99)

Recommendations

• Carry-free addition of recoded binary signed-digit numbers
• A Nonspeculative Maximally Redundant Signed Digit Adder
• An improved maximally redundant signed digit adder
• Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains
• Redundant arithmetic, algorithms and implementations

Cited in

(6)

• Redundant arithmetic, algorithms and implementations
• A Nonspeculative Maximally Redundant Signed Digit Adder
• Logic Design of a Fast Circuit for Iterative Additions in Redundant Hybrid Number Systems
• Design and Implementation of Modified Signed-Digit Adder
• Design of multiple-valued arithmetic circuits using counter tree diagrams
• An improved maximally redundant signed digit adder

This page was built for publication: A signed binary addition circuit based on an alternative class of addition tables

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1860062)