Accelerating lattice reduction with FPGAs

DOI10.1007/978-3-642-14712-8_8MaRDI QIDQ3584979zbMATH OpenOpenAlexFDO

Authors Jérémie Detrey, Guillaume Hanrot, Xavier Pujol, Damien Stehlé

Publication date 31 August 2010

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-14712-8_8

zbMATH Keywords

Euclidean latticesFPGAShortest Vector Problem

Mathematics Subject Classification ID

Number-theoretic algorithms; complexity (11Y16) Symbolic computation and algebraic computation (68W30) Cryptography (94A60)

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Cited in

(6)

• Hardware reduction for LUT-based Mealy FSMs
• Algorithms for the shortest and closest lattice vector problems
• Analysis of Gauss-sieve for solving the shortest vector problem in lattices
• A Parallel Implementation of GaussSieve for the Shortest Vector Problem in Lattices
• Another 80-dimensional extremal lattice
• I/O overhead and parallel VLSI architectures for lattice computations

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