Analog property checkers: a DDR2 case study

DOI10.1007/S10703-009-0085-XMaRDI QIDQ5962118zbMATH OpenOpenAlexFDO

Authors Kevin D. Jones, Victor Konrad, Dejan Ničković

Publication date 16 September 2010

Published in Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL https://openaccess.city.ac.uk/id/eprint/1066/1/ddr2-journal.pdf

zbMATH Keywords

analogcase studymixed-signalmonitoringproperty checkerstemporal logic

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

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Cites work

• Automated Technology for Verification and Analysis
• Checking Temporal Properties of Discrete, Timed and Continuous Behaviors
• Formal Techniques, Modelling and Analysis of Timed and Fault-Tolerant Systems
• scientific article; zbMATH DE number 1670567 (Why is no real title available?)
• scientific article; zbMATH DE number 1670781 (Why is no real title available?)
• scientific article; zbMATH DE number 1670800 (Why is no real title available?)
• scientific article; zbMATH DE number 1796123 (Why is no real title available?)
• scientific article; zbMATH DE number 1903367 (Why is no real title available?)
• scientific article; zbMATH DE number 868107 (Why is no real title available?)
• scientific article; zbMATH DE number 1405643 (Why is no real title available?)
• Temporal Logic Verification Using Simulation
• Test Coverage for Continuous and Hybrid Systems
• The benefits of relaxing punctuality

Cited in

(3)

• Parameter synthesis of polynomial dynamical systems
• System design of stochastic models using robustness of temporal properties
• Parameter synthesis through temporal logic specifications

Describes a project that uses

Uses Software

• FoCs
• JPAX
• LTL2BA
• AMT

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