Architecture technique trade-offs using mean memory delay time

DOI10.1109/12.543704MaRDI QIDQ4420822zbMATH OpenOpenAlexFDO

Authors Chungho Chen, Arun K. Somani

Publication date 1996

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://semanticscholar.org/paper/dc0abcb986d36fc7de29bfe574d6e9ad31ac6748

zbMATH Keywords

cache-based systempipelined memory

Mathematics Subject Classification ID

Computer system organization (68M99)

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Cited in

(2)

• Time-memory-processor trade-offs
• Memory latency effects in decoupled architectures

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