Aggressive memory-aware compilation
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Cited in
(7)- Improving effective bandwidth through compiler enhancement of global cache reuse
- Using FORAY models to enable MPSoC memory optimizations
- Architecture technique trade-offs using mean memory delay time
- scientific article; zbMATH DE number 2017363 (Why is no real title available?)
- Exploiting on-chip memory bandwidth in the VIRAM compiler
- scientific article; zbMATH DE number 5049786 (Why is no real title available?)
- Improving memory traffic by assembly-level exploitation of reuses for vector registers
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