Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver

DOI10.1007/978-3-540-75596-8_7MaRDI QIDQ3510788zbMATH OpenOpenAlexFDO

Authors David Walter, Scott Little, Chris J. Myers

Publication date 3 July 2008

Published in Automated Technology for Verification and Analysis (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-540-75596-8_7

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Recommendations

• Automated Technology for Verification and Analysis
• Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking
• Formal Methods in Computer-Aided Design
• Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces
• Analog/mixed-signal circuit verification using models generated from simulation traces

Cites work

• Automated Technology for Verification and Analysis
• Computer Aided Verification
• Computer Aided Verification
• Formal Methods in Computer-Aided Design
• scientific article; zbMATH DE number 1956569 (Why is no real title available?)
• scientific article; zbMATH DE number 1903367 (Why is no real title available?)
• Logic for Programming, Artificial Intelligence, and Reasoning
• Model Checking Software
• On hybrid Petri nets
• Solving SAT and SAT modulo theories, from an abstract Davis-Putnam-Logemann-Loveland procedure to \(\operatorname{DPLL}(T)\)
• Theory and Applications of Satisfiability Testing
• Tools and Algorithms for the Construction and Analysis of Systems

Cited in

(7)

• Generalized rewrite theories, coherence completion, and symbolic methods
• Rewriting modulo SMT and open system analysis
• Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces
• scientific article; zbMATH DE number 177501 (Why is no real title available?)
• Automated Technology for Verification and Analysis
• Formal Methods in Computer-Aided Design
• Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking

This page was built for publication: Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3510788)