Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces
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Cites work
- Automated Technology for Verification and Analysis
- Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver
- Formal Methods in Computer-Aided Design
- scientific article; zbMATH DE number 1903367 (Why is no real title available?)
- Hybrid Systems: Computation and Control
- On hybrid Petri nets
- Temporal Logic Verification Using Simulation
Cited in
(8)- Simulation-based hardware verification with a graph-based specification
- Simulation and Verification of Electronic and Biological Systems
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- Analog/mixed-signal circuit verification using models generated from simulation traces
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- Formal Methods in Computer-Aided Design
- On simulation-based probabilistic model checking of mixed-analog circuits
- Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking
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