Bubble partitioning for LUT-based sequential circuits

DOI10.1007/3-540-44687-7_35MaRDI QIDQ4786136zbMATH OpenFDO

Authors Frank Wolz, Reiner Kolla

Publication date 12 December 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2147/21470336

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computing methodologies and applications (68U99)

Recommendations

• Technology mapping and placement for delay-minimization in LUT-based FPGA design
• A new placement method for direct mapping into LUT-based FPGAs
• Implementing and clustering modules with complex delays
• On nominal delay minimization in LUT-based FPGA technology mapping
• On the set of target path delay faults in sequential subcircuits of lUT-based FPGAs

Cited in

(3)

• Technology mapping and placement for delay-minimization in LUT-based FPGA design
• On nominal delay minimization in LUT-based FPGA technology mapping
• Exploiting reconfigurability for effective testing of delay faults in sequential subcircuits of lUT-based FPGAs

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