A new placement method for direct mapping into LUT-based FPGAs

DOI10.1007/3-540-44687-7_4MaRDI QIDQ4786085zbMATH OpenFDO

Authors Joerg Abke, Erich Barke

Publication date 12 December 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2147/21470027

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computing methodologies and applications (68U99)

Recommendations

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Cited in

(8)

• Technology mapping and placement for delay-minimization in LUT-based FPGA design
• Integrated iterative approach to FPGA placement
• A novel watermarking technique for LUT based FPGA designs
• A placement/routing approach for FPGA accelerators
• scientific article; zbMATH DE number 1979560 (Why is no real title available?)
• Tightly integrated placement and routing for FPGAs
• Bubble partitioning for LUT-based sequential circuits
• Deep-learning-based FPGA fast placement algorithm

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