Integrated iterative approach to FPGA placement

DOI10.1007/3-540-46117-5_27MaRDI QIDQ4407333zbMATH OpenFDO

Authors Martin Danek, Zdenek Muzikár

Publication date 29 June 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2438/24380253.htm

Mathematics Subject Classification ID

Computing methodologies and applications (68U99)

Recommendations

• Tightly integrated placement and routing for FPGAs
• A new placement method for direct mapping into LUT-based FPGAs
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Cited in

(9)

• Technology mapping and placement for delay-minimization in LUT-based FPGA design
• Concurrent placement and routing in the design of integrated circuits
• A placement/routing approach for FPGA accelerators
• A new placement method for direct mapping into LUT-based FPGAs
• Tightly integrated placement and routing for FPGAs
• Gambit: A tool for the simultaneous placement and detailed routing of gate-arrays
• Deep-learning-based FPGA fast placement algorithm
• A Constraint Satisfaction Approach for Programmable Logic Detailed Placement
• Resource sharing combined with layout effects in high-level synthesis

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