Compact hardware for computing the Tate pairing over 128-bit-security supersingular curves

DOI10.1007/978-3-642-17455-1_25MaRDI QIDQ3059665zbMATH OpenOpenAlexFDO

Authors Nicolas Estibals

Publication date 26 November 2010

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.230.2637

zbMATH Keywords

FPGA implementationsupersingular elliptic curvesTate pairing

Mathematics Subject Classification ID

Applications to coding theory and cryptography of arithmetic geometry (14G50) Cryptography (94A60)

Recommendations

• High speed cryptoprocessor for \(\eta _{T }\) pairing on 128-bit secure supersingular elliptic curves over characteristic two fields
• Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
• FPGA and ASIC implementations of the \(\eta _T\) pairing in characteristic three
• Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves
• Hardware architectures for the Tate pairing over GF\((2^{m})\)

Cited in

(7)

• Hardware architectures for the Tate pairing over GF\((2^{m})\)
• Optimal Eta Pairing on Supersingular Genus-2 Binary Hyperelliptic Curves
• Parallelizing the Weil and Tate pairings
• High speed cryptoprocessor for \(\eta _{T }\) pairing on 128-bit secure supersingular elliptic curves over characteristic two fields
• Towards Faster and Greener Cryptoprocessor for Eta Pairing on Supersingular Elliptic Curve over $\mathbb{F}_{2^{1223}}$
• Decentralized attribute-based signatures
• Fast Architectures for the \eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves

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